Job ID FS0001
Location Bangalore
Experience 3+ Years 

Overview

We are looking for a Physical Verification Engineer with over 3 years of experience in performing LVS, DRC, ERC, Antenna and other signoff checks at block or chip level. The ideal candidate should have hands-on experience with industry-standard EDA tools and a strong understanding of digital and mixed-signal layout verification.

Responsibilities

1. Perform DRC/LVS/ERC/Antenna/XOR checks at block-level and top-level.

2. Debug and resolve physical verification issues in collaboration with the layout and design teams.

3. Develop and maintain PV rule decks and flows.

4. Work on foundry rule decks (TSMC/Samsung/Intel/GlobalFoundries) and ensure signoff compliance.

5. Automate verification flows using scripting (TCL/Perl/Python).

6.Support physical design and layout teams with timely feedback and closure of PV violations.

7. Collaborate with cross-functional teams across geographies for tapeout activities.

8. Experience in FinFET/advanced technology nodes (7nm/5nm/3nm) is a plus.

9. Good understanding of GDS/OASIS formats, layout hierarchies, and verification flows.

General Requirments

1.Experience in working with international clients or multi-site teams.

2. Exposure to analog-mixed signal (AMS) verification is a plus.

3. Strong debugging and problem-solving skills.

4. Excellent interpersonal skills, including written and verbal communication

Scripting Languages

1.TCL, Perl, or Python

Tools

Calibre, ICV, Pegasus,

Layout tools like Virtuoso or Innovus