Job ID FS0002
Experience 3+ Years
Location Bangalore

Overview

We are seeking a skilled Physical Design Engineer with 3+ years of hands-on experience in ASIC backend flow from RTL to GDSII. The ideal candidate should have a strong understanding of STA, floorplanning, clock tree synthesis, routing, and sign-off processes.

Responsibilities

1.Execute full RTL-to-GDSII flow including floor planning, placement, CTS, routing, and signoff.

2. Work on hierarchical and flat designs using advanced nodes (7nm, 5nm, or below).

3. Handle design partitioning, power planning, IR/EM analysis, and timing closure.

4. Perform STA, congestion analysis, DRC/LVS fixing in collaboration with PV team.

5. Collaborate with RTL designers and verification teams for design convergence.

6. Work with EDA tools like Innovus, ICC2, Primetime, Voltus, RedHawk etc.

7. Develop and maintain scripts (TCL, Perl, Python) for design automation.

8. Good understanding of power domains (UPF/CPF) and low-power design techniques.

9. Experience with timing closure, power planning, floor planning, and sign-off.

General Requirements

1 Strong debugging skills across timing, congestion, and physical violations.

2 Familiarity with clock tree synthesis and advanced routing methodologies.

3 Experience with FinFET technology nodes (7nm/5nm/3nm).

4 Exposure to low power design, EM/IR analysis, and DFT is a plus.

5 Strong communication and collaboration skills.

Scripting Languages

1 TCL, Perl, or Python.

Tools

1.Cadence Innovus, Synopsys ICC2, and Primetime.