Experience : 3+ Years 
Location : Bangalore

Overview

We are looking for a skilled Synthesis Engineer with a strong foundation in RTL-to-gate-level synthesis, logic equivalence checking, and timing optimization. The ideal candidate will have hands-on experience with industry-standard EDA tools and a good understanding of timing constraints and low-power design methodologies.

Responsibilities

1.Knowledge and exposure to Synthesizable Verilog / System Verilog.

2.”DFT insertions that include MBIST and SCAN, setup Timing Constraints for functional and Test Modes, and Validation.”

3 “Good knowledge of VLSI, Digital electronics and understanding of semiconductor devices, circuits, timing closure of digital design.”

4 Expertise in the overall chip design implementation process, and working experience with ASIC design methodologies, usage of EDA tools, and/or CAD engineering

5 “Good understanding of timing concepts and expected to analyze the constraint used for design and its impact on timing closure.”

6 “Proficiency in top-level Integration issues to ensure block level deliverables meet project level requirements for timing and layout closures.”

7 Timing analysis with STA tools Constraints debug and sanity checks 

8 Understanding of IP and SoC design and implementation methodology and challenges

9 Strong knowledge of RTL2GDSII flow with strong fundamentals in digital design & implementation. 

General Requirments

1 Researching and innovating solutions in known and unknown areas. 

2 Should be independent and open to learn tools/technologies on the go.

3 Excellent communication skills, verbal and written; ability to produce design documents detailing product requirements. 

4 Excellent systematic and problem-solving skills with the ability to clearly narrow down and summarize findings

Scripting Languages

1 “Perl, TCL, Makefile, Shell & Knowledge on  C, C++

Tools

1 “Fusion Compiler, Synopsys Design Compiler and innovus”.