Job ID: FS0004
Experience: 3
Location Bangalore

Overview

We are looking for a talented STA Engineer with over 3 years of experience in performing static timing analysis, working across multi-voltage, multi-mode, and multi-corner (MVMMMC) environments. The ideal candidate will have hands-on expertise in timing closure, constraint development, and debugging timing violations in synthesis and physical design stages.

Responsibilities

1 Basic understanding of device electronics, digital design, logic synthesis, timing analysis, physical design.

2 ” Take ownership of designing and implementing SDC for complex SoC architectures.”

3 Understanding CTS strategies, LVF/POCV variations and providing feedback to the implementation/methodology teams.

4 Hands-on experience of working on technology nodes like 28nm, 20nm, 14nm, 10nm

5 Hierarchical timing analysis and convergence at block, section and fullchip level.

6 Understanding of one or more of design flows like Synthesis, Constraint development and STA (Functional and DFT modes) and Physical Design

7 Thorough understanding of test-mode constraints and DFT8 Knowledge of low-power techniques including clock gating, power gating and MV designs

Protocol

1 DDR1/2/3, SDR, LPDDR, Flash, SPIs, Ethernet, USBHS, USBFS, JTAG, Display etc.

General Requirments

1 Strong analytical and problem-solving skills to address timing-related challenges effectively.

2 Excellent interpersonal skills, including written and verbal communication

3 Self-motivator with strong problem-solving skills

4 Strong knowledge on constraints development and validation.

Scripting Languages

1 ” Perl, Tcl, Python, Awk”.

Tools

1 Primetime, Tempus, CC2, Innovus, RC, DC, PT, PTSI