Job ID: FS0005
Experience: 3+ years
Location: Bangalore

Overview

We are looking for an experienced Formal Verification Engineer with a solid understanding of assertion-based verification, formal property checking, and equivalence checking. The ideal candidate will contribute to improving design reliability and safety using formal methods in collaboration with design and DV teams.

Responsibilities

1 Identify blocks suitable for applying Formal Verification

2 Knowledge of Hardware Description and Verification Languages, such as VHDL, Verilog/ System Verilog

3 Familiarity with hardware description languages (HDL) and digital design verification.

4 Applying various FV techniques to reduce complexity and prove correctness of DUT.

5 Debugging RTL to identify causes of failure scenarios.

6 Understanding of the end-to-end verification processes, from test plan creation through to verification closure

7 Guide and train team members on effective usage of Formal Verification tools

8 Knowledge of relevant industry standards and best practices in formal verification.

General Requirments

1 Excellent problem-solving skills and attention to detail.

2 Effective communication skills and the ability to collaborate in a team environment.

3 Creativity and ability to communicate ideas effectively

4 Good interpersonal and teamwork skills!

Scripting Languages

1 Python/Perl/TCL/shell programming

Tools

1 “SMT solvers, model checkers, VC Formal, Jasper Gold